1. Field of the Invention
Generally, the present invention relates to video display systems. More specifically, the present invention relates to systems and methods for scaling a two-dimensional (2D) video image.
2. Description of the Related Art
Video display devices, such as cathode ray tubes (CRTs), plasma monitors, liquid crystal displays (LCDS) and liquid crystal on silicon (LCoS) displays, typically require a scaling function to perform properly. The scaling function enables the source video images, or frames, of a fixed size and/or aspect ratio to be shown and viewed on a particular display device with a different size and/or aspect ratio. Thus, the scaling function can scale the resolution of the source image to match the resolution used by the display device. Scaling can be accomplished in either the horizontal or vertical dimensions, or both, and can be either upscaling or downscaling, or both.
FIG. 1 illustrates a typical scaling function. As shown in FIG. 1, an input image and associated blanking areas 110 can be enlarged using an upscaling function 120 to an output image 130 appropriate for a particular display device. As used herein, each of the input image and output image can be deconstructed into a number of input lines, each input line including a number of data points. While not meant as a limiting definition for the invention, the input lines are typically horizontal lines that are aligned lengthwise in a vertical direction. The total number of vertical lines, or rows, can be referred to as the vertical resolution. The horizontal points in each line can include picture element, or pixel, data for displaying on a video display device. The horizontal points can also include blanking area information as is generally known in the art.
In the typical scaling device, the pixel data of the source image is received at an input clock rate of the source image, while that of the resulting display image is produced at an output clock rate. Modern scalers use the input clock of the source image as the clock source for a phase lock loop (PLL) to generate the output clock for the display image. This ensures that the input frame rate is equal to the output frame rate. By making the output clock directly related to the input clock, the typical scaler is able to work with just a few line buffers instead of using a larger memory, such as a frame buffer. However, the output clock of the typical scaling device can deviate from the desired display frequency due to inaccuracies of the PLL (i.e., the output clock is not in perfect proportion to the input clock). Such output clock deviation can cause the limited number of line buffers to be insufficient to ensure correct action of the scaler, resulting in incorrect image output.
Additionally, if the PLL uses the input clock to generate the output clock, the output clock must change with the input clock. Generally, the input clock can be unstable under certain operating states of the video display device, such as, fast forward, fast rewind, slow motion, and so on. In this case, the input clock can have a very large variance, which the output clock would duplicate. This unstable, large variance output clock can produce unstable horizontal and vertical sync signals (HS, VS), which can cause the video display device to produce unstable frames or be completely unable to deliver a frame at all.
FIG. 2 illustrates a typical video display scaling device. This typical video display scaling device includes a line buffer block 210 that receives the input data and sync signals. The input clock, ICLK, used with the input data and sync signals is provided to a phase lock loop (PLL) 220. PLL 220 provides an output clock, OCLK, for use by the remainder of the scaling device. The output of line buffer block 210 is coupled to the input of a FIFO block 230. The output of FIFO block 230 is coupled to an interpolator line buffer block 240 and to a scaler block 250. The output of interpolator line buffer block 240 is also coupled to scaler block 250. The output of scaler block 250 is the output data and sync signals.
As shown in FIG. 2, the source data input clock, ICLK, is used by PLL 220 to generate the output clock, OCLK. Thus, in the typical video scaling device, the input data rate must be equal to the output data rate. This equality can be represented by the following equation.Htotal—i×Vtotal—i×ICLK=Htotal—o×Vtotal—o×OCLK  (1)In equation (1): Htotal_i represents the total horizontal points of the input image (including effective points and blank points); Vtotal_i represents the vertical resolution of the input image; Htotal_o represents the total horizontal points of the output image (including effective points and blank points); and Vtotal_o represents the vertical resolution of the output image.
To establish equation (1) (i.e., input data rate=output data rate), the ratio of the output clock to the input clock must satisfy the following equation.OCLK=(Htotal—i×Vtotal—i×ICLK)/(Htotal—o×Vtotal—o)  (2)At the required ratio of equation (2), the output frame rate is equal to the input frame rate at any given time. Each frame rate can then be defined by the following equations.Output frame rate=1/(Htotal—o×Vtotal—o×OCLK)  (3)Input frame rate=1/(Htotal—i×Vtotal—i×ICLK)  (4)
Due to inaccuracies of PLL 220, however, the output clock will deviate from the targeted, or ideal, output frequency; that is, a perfect ratio of the input clock to the output clock cannot be obtained. Such output clock deviation will cause the line buffers 210 to become unable to ensure correct action of the scaler; hence, incorrect video output will result.
For the scaling device of FIG. 1, consider the example of scaling up a 640×480 (i.e., horizontal line length×vertical number of lines) input image to a 960×720 output image. For equation (1) to be satisfied, the time it takes to write 480 input lines must be the same as that to read 720 output lines; or more simply put, the time required to write 2 input lines must be the same as that required to read 3 output lines. Assuming the upscaling adopts a bi-linear algorithm (i.e., that each output line is obtained by inputting two lines) and a single port SRAM is used, the scaling device of FIG. 1 needs at least 4 line buffers to allow the scaler to work properly.
However, as previously mentioned, if equation (1) is not satisfied due to inaccuracy of the PLL, then the time required to write 2 input lines will not equal that required to read 3 output lines. This situation can be illustrated by the following equations.OCLK≠(Htotal—i×Vtotal—i×ICLK)/(Htotal—o×Vtotal—o)  (5)OCLK=(Htotal—i×Vtotal—i×ICLK)/(Htotal—o×Vtotal—o)+(t′)  (6)As shown by equations 5 and 6, t′ represents an increment of time by which the input frame is different from the output frame and may have either a positive or negative value. If t′ is positive, the time required to read 3 output lines is longer than the time to write 2 input lines (i.e., the rate at which 2 input lines are written is higher than the rate at which 3 output lines are read). The discrepancy adds up until an input line is written into a line buffer without the previous data of that line buffer having been read; that is, an unread input line is overwritten. This will result in an incorrect output image. If t′ is negative, the time required to write 2 input lines is longer than the time to read 3 input lines (i.e., the rate at which 3 output lines are read is higher than the rate at which 2 input lines are written). In this case, as t′ additively becomes more negative, an output line will eventually read old, duplicative data from a line buffer before a new input line can be written into that line buffer, resulting in inaccurate data reading.
An additional deficiency of the typical scaling device that uses the source image input clock to generate the output clock is that the output clock must change with the input clock. Typically, under certain scaling conditions (e.g., fast forward, fast rewind, or slow motion from a video display device), the input clock can have a very large variation and can become unstable. At that time, the output clock follows the input clock and can generate unstable horizontal and vertical sync signals to the output frame. In this case, the two signals can have a high variation and cause the display device, such as a CRT, to produce unstable frames, or be unable to deliver images at all.
Therefore, what is needed is a scaling device for video displays that produces stable output frames using a limited number of line buffers without the PLL inaccuracies associated with the typical scaling device.